According to this library, you need to set the clock high before enabling the slave select line, otherwise it creates a clock glitch. The executable application and full project code in Delphi are provided. Sign up using Facebook. We got it working. Some customers have tried using 3 phase clocking, but have not been successful.
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Source code and executable are available for free download. It required two areas of modifications compared to a straightforward implementation.
FTDI MPSSE USB smart cable
Hackish work around to properly support SPI mode 1. Sign up or log in Sign up using Google. Ffdi update this answer when we determine feasibility. Home Questions Tags Users Unanswered. The following examples on this page illustrate how to achieve this for several popular protocols:. I got a response from FTDI technical support: Post as a guest Name. The executable application and full project code in Delphi are provided.
We got it working. This capture by a Saleae Logic Pro 8 v 1. Both digital and analog versions of each SPI line are shown for thoroughness. I am not sure what to make ftxi the situation.
The software is changed with adding slightly odd but careful ordering of chip select and clock transitions. The executable application and full project code are provided. The following examples on fhdi page illustrate how to achieve this for several popular protocols: Some customers have tried using 3 phase clocking, but have not been successful.
FTDI FT2232H USB to UART/MPSSE/JTAG Breakout Board
Unfortunately it is interpreted and shown as 0x40 0x Your decoded data is shifted right, which is exactly the glitch this comment is describing Hackish work around to properly support SPI mode 1.
Your decoded data is shifted right, ctdi is exactly the glitch this comment is ftxi. That appears to definitively answer the question of how to do this. We are looking at possible workarounds such as inverting the clock signal in hardware. The sequence to enable chip select is: Download the project documentation and schematic in PDF format by clicking here. The disable CS step then corrects this, ready for the next CS enable sequence when it is eventually time.
TI have a JTAG learning tool and accompanying abstract available on their website which is available for free download. According to this library, you need to set the clock high before enabling the slave select line, otherwise it creates a clock glitch. However, the device to be written to only does Mode 1 see 9. A separate page has been created where the LibMPSSE library can be downloaded, along with code examples and release notes.
At the end of a message, it does produce a tiny clock glitch, but none of our devices Saleae analyzer and TI A2D converters care. I ftci the signals doing what I think needs to be done, but the Saleae analyzer complains with The initial idle state of the CLK line does not match the settings.